Low-voltage Power-efficient Dynamic Latched Comparator
نویسندگان
چکیده
A new dynamic comparator is presented using modified gain stage followed by latch stage for high speed analog-to-digital converter. The gain stage of proposed comparator is a modified class AB pre-amplifier which makes it suitable for high speed of operation with small delay time and low power. The circuit is simulated in 180 nm process technology using tool Cadence Virtuoso with a supply voltage of 1.2V operating at maximum sampling frequency of 2 GHz. After simulation the circuit results shows that it has 323.0 pS delay time and 38.99 μW power for common mode voltage Vcm = 0.7 , input differential voltage (∆Vin = 1 mV) operating at sampling frequency of 500 MHz at 1.2 V supply voltage. Simulation results confirms that the proposed comparator considerably reduces the delay and power consumption Keywords— Analog-to-digital convertor (ADC), sense amplifier (SA), pre-amplifier, Latched comparator, Low voltage, Clock sampling frequency.
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